ZAMC4100 Datasheet, PDF (91/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
3.12.9. ADC Comparator and Counter
The ZAMC4100 features a 10-bit result comparator that allows continuous ADC running and signed result
comparison within the SBC. After each conversion, the ADC comparator checks the result for being less than or
greater than a pre-configured value. If the result of the comparison is TRUE, the comparator counter is
incremented. If the result is FALSE, the counter value is decremented or cleared depending on the value of the
CNTDEC bit in the ADCCMPH register (Table 3.42). When the comparator counter value reaches the value
programmed in the RCMPCNT register (Table 3.50), a comparator interrupt is generated and indicated in the
ADCCMPIF flag in the ADCSTAT register (Table 3.39).
Using the ADC comparator together with the counter allows filtering out the short-term deviations in the measured
analog values (currents, voltages, positions, etc.).
Note: When the comparator is enabled (bit CMPEN = ‘1’), the ADCRDYIF flag is automatically masked. In this
way, the global ADC interrupt (see Figure 3.8) is not always generated at the end of every conversion cycle, only
when a valid comparator event is detected.
Signed or Unsigned Comparison
Whether the results are signed or unsigned in ADC comparator mode is determined automatically depending on
the type of the ADC conversion and the value of the RESSIGN bit (see section 3.12.8). When the ADC performs
ratiometric conversion, the ADC comparison runs in signed mode if bit RESSIGN = 1 and in unsigned mode if
RESSIGN = 0. For absolute or temperature ADC conversion, the comparator performs unsigned results
comparison.
ADCCMPH and ADCCMPL Registers
These registers are used for configuring the comparator mode and threshold value. The bits of both registers are
described in Table 3.42. The reset values for registers ADCCMPH and ADCCMPL are 00_HEX.
Note: When the ADC conversion is running, WRITE access to registers ADCCMPH and ADCCMPL is disabled.
Table 3.42 ADCCMPH and ADCCMPL Bits Description
Bit Description
Register ADCCMPH
CMPEN: Comparator enable bit.
7 1 = The comparator is enabled.
0 = The comparator is disabled.
CMPMD: Comparison mode bit.
6 1 = The comparison returns TRUE if the ADC result is less than the programmed value.
0 = The comparison returns TRUE if the ADC result is greater than or equal to the programmed value.
CNTDEC: Determines the comparator’s counter decrement behavior.
5 1 = When the comparison returns FALSE, the counter value is decremented by one.
0 = When the comparator returns FALSE, the counter value is cleared.
4:2 Unimplemented bits. Read as 0.
1:0 CMPTH[9:8]: Bits 9:8 of the ADC comparator threshold value.
Register ADCCMPL
7:0 Bits 7:0 of the ADC comparator threshold value.
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January 26, 2016