ZAMC4100 Datasheet, PDF (30/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
2.7. LIN Interface
The ZAMC4100 features a LIN slave interface with hardware resources covering the physical and data link
communication layers (see Figure 2.2). The network layer must be implemented as part of the MCU firmware.
The LIN PHY is built into the SBC chip and is LIN2.0/2.1 compatible. It supports LIN wake-up detection, short-
circuit detection/protection and dominant time-out detection/protection. All events are captured as interrupt flags in
the SBC interrupt controller, and the MCU can access them via the SPI interface.
Figure 2.2 ZAMC4100 LIN Interface and Open Systems Interconnection (OSI) Layers Coverage
OSI Model
PACKETS
FRAMES
BITS
NETWORK
Path Determination &
Logical Addressing
DATA LINK
Physical Addressing
PHYSICAL
Media, Signal & Binary
Transmission
MCU: Firmware
(LIN Protocol Engine)
MCU: LIN Controller
SBC: LIN PHY,
Wake-up, Diagnostics
The block diagram in Figure 2.3 shows the ZAMC4100 LIN interface structure and the partitioning between the
SBC and MCU chips. The hardware for covering the LIN data link layer is implemented in the MCU chip as a LIN
controller. The MCU LIN controller features a UART module for the LIN frame generation, BREAK/SYNC
detection fields, and LIN bus inactivity timer.
Figure 2.3 LIN Slave Node Implementation in the ZAMC4100
SBC Chip
LIN PHY
LIN
TX
sh _pd
RX
sh = short
pd = power down
LIN Wake-up
Diag & Ctrl
TXD _{LIN Pwr Crtl}
RXD
LIN Short
(debounced)
Dominant
Time-Out
LIN Wake-up
TXD
RXD
TXD
RXD
MCU Chip
LIN Controller
UART
BREAK/SYNC
Detection
Inactivity Timer
(4 sec)
© 2016 Integrated Device Technology, Inc.
30
January 26, 2016