ZAMC4100 Datasheet, PDF (122/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
4.9.6. General Remarks for SW-LIN Usage
Here is a short summary of how to handle the SW-LIN:
• At power-up, the receiver is not completely disabled, but the inactivity timer is disabled.
• When the inactivity timer is needed, it has to be enabled.
• When the system clock divider will be changed, both the receiver and the inactivity timer must be disabled
by writing 0x2 or 0x6 to the Z1_LINCFG register.
• When the system clock will be switched off, both the receiver and the inactivity timer must be disabled by
writing 0x2 or 0x6 to the Z1_LINCFG register.
• It is in the responsibility of the software that switching to transmit happens in accordance with the LIN
protocol.
• If there is no need to receive the data following the PID, software should stop the receiver by writing 0x1 or
0x5 to the Z1_LINCFG register.
• If data will be transmitted after reception of the PID, software can also stop the receiver by writing 1_HEX or
5_HEX to the Z1_LINCFG register. However, the receiver is also stopped by writing data to be transmitted
into the TX buffer.
• The baud rate must not be written as it is automatically set by the BREAK/SYNC field detector. The only
exception is in debugging mode, when the receiver is fully disabled and the SW-LIN will operate as a TX
UART.
• The protocol is handled in software. Although the receiver is stopped and is waiting for a new sync strobe
when the STOP bit is zero (this situation is possible when the MASTER changes the baud rate), it is also
possible that a SYNC field is detected as a correct byte when the master has increased the baud rate and
the receiver samples the data line for the STOP bit when the RXD line is high; e.g., during transmission of
the SYNC field. Therefore software must ignore all received bytes (but clear the buffer) after the checksum
has been received until a new synchronization has occurred (interrupt SYNCDET). To avoid this, software
can also stop the receiver by writing 1 to the STOPRX bit in Z1_LINCFG. Then the receiver does not
receive anything before a new synchronization has occurred.
4.9.7. SW-LIN Registers
The following registers are used by the SW-LIN module:
• Z1_LINCFG SW-LIN configuration register (Table 4.25)
• Z1_LINDATA READ/WRITE access to this register accesses the LIN RX data buffer and TX data
buffer respectively (Table 4.27)
• Z1_LINIRQEN Interrupt enable register (Table 4.28)
• Z1_LINSTAT Interrupt status register (Table 4.26)
• Z1_LINBAUDHIGH:Z1_LINBAUDLOW: Baud rate value for LIN interface (Table 4.30 and Table 4.29)
For detailed register address mapping and bits description, refer to section 4.10.5.
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January 26, 2016