ZAMC4100 Datasheet, PDF (86/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
Table 3.37 ADCCONF Register Bits Mapping
Name
ADCCONF
Bit No
7
6
5
4
3
2
1
0
Bit name
Reset
U
U
0
0
0
0
0
0
Access
U
U
R/W R/W R/W R/W R/W R/W
Address
0x11
R/W = Read/Write bit; U = Unimplemented, read as ‘0.’
Note: When the ADC conversion is running, the ADCCONF register is accessed as read-only.
Table 3.38 ADCCONF Register Bits Description
Bit Description
7:6 Unimplemented bits. Read as 0.
RESJSTF: Result register justification format. Details provided in section 3.12.8.
5 1 = Right-justified result in ADCRESx.
0 = Left-justified result in ADCRESx.
RESSIGN: Result register in signed or unsigned format.
4 1 = Signed value (RESCODE = -512 to +511 full-scale range).
0 = Unsigned value (RESCODE = 0 to 1023 full-scale range).
CCNVMD: Continuous conversion versus ADC result register read mode.
3 ^{1 = After ADC sample, halt next ADC sample operation until ADCRESx register is read.}
0 = After ADC sample, proceed to next ADC sample operation regardless of whether the ADCRESx register has
been read or not. This means that the ADCRESx register will be overwritten by the next conversion result.
2:0 ADCSR: Sample rate configuration (see Table 3.41).
© 2016 Integrated Device Technology, Inc.
86
January 26, 2016