ZAMC4100 Datasheet, PDF (151/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
Pin Name
Position
Purpose
Mode
Description
TEST INTERFACE
TEST
50
TRSTN
49
Digital
Digital
In
Global test enable pin; connect this pin to
GND in application
In
JTAG low-active reset
TCK
48
Digital
In
JTAG clock
TMS
47
Digital
In
JTAG mode select
TDO
46
Digital
Out
JTAG data out pin
TDI
45
Digital
In
JTAG data in pin
STO
n.c.
52
18,19,
22,36,63
Digital
-
Out
SBC test data out; leave this pin open in
the application
-
Not bonded package pins; connect them to
ground
(1) The ground connections of the ZAMC4100 on the PCB should be separated into three specific planes for ground decoupling and
better noise immunity:
• Analog ground: VSSA, S_N, CAP_5V0 (ground plate)
• Digital ground: VSSD1, VSSD2, VSS_IO, VSS_LIN, CAP_3V3 (ground plate), CAP_1V8 (ground plate), CAP_MCU (ground
plate)
• Power ground: VSS1 to 5
All three ground planes must be connected to pin 65 (ZAMC4100 exposed pad), which must be a single common GND point on
the PCB.
(2) In the application, the exposed pad (pin 65) must be connected to ground.
(3) Do not supply any external circuitry via these pins.
(4) If the S_N pin is not used for supplying sensors, it must be connected to the GND rail on the PCB.
(5) All unused ADC inputs (pins AIN1 to 4) and GPIO ports (pins GPIO0 to 7) can be left open or grounded for better EMI.
© 2016 Integrated Device Technology, Inc.
151
January 26, 2016