ZAMC4100 Datasheet, PDF (125/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
SYS_RSTSTAT
Bit
NAME
7
ENLOCKUP
ADD: 0x4000_000C
Ext.
Int. Reset
Access Access Value
R
R
0
7 : 0 SETENLOCKUP W
---
0
15:8
---
R
23 : 16 JTAGRSTREQ W
31 : 24
---
R
---
0
R
0
---
0
Description
This bit reflects whether a lockup from the ARM® core is
allowed to reset the system (set to 1) or not (set to 0).
To enable the lockup reset, 0xC9 must be written to bits 7:0.
It can be disabled by writing another value. This bit is reset by
all four reset sources (extRst, sysRstReq, lockupRst,
jtagRst).
Unused; always read as 0.
To generate a reset via the JTAG interface, 0x3A must be
written to bits 23:16. These bits cannot be written by the
ARM® core.
Unused; always read as 0.
4.10.2. GPIO Registers
The GPIO registers are mapped into the system address space between 0x4000_1400 and 0x4000_17FF.
Unused addresses must not be accessed.
Table 4.9 Register [0x4000_1400] GPIO_DIR
GPIO_DIR
ADD: 0x4000_1400
Bit
Name
Ext.
Int. Reset
Access Access Value
7:0
GPIODIR
R/W
R
0
15 : 8
---
31 : 16
---
N/A
N/A
0
R
---
0
Description
1: GPIO pin is switched as output direction.
0: GPIO pin is switched as input direction.
Reserved.
Unused; always read as 0.
Table 4.10 Register [0x4000_1404] GPIO_IN
GPIO_IN
ADD:0x4000_1404
Bit
Name
Ext.
Int. Reset
Access Access Value
7:0
GPIOIN
R
R/W
0
15 : 8
---
N/A
N/A
0
31 : 8
---
R
---
0
Description
Synchronized input value.
Reserved.
Unused; always read as 0.
© 2016 Integrated Device Technology, Inc.
125
January 26, 2016