ZAMC4100 Datasheet, PDF (48/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
Table 3.6 SMDCTRL Register Bits Description
Bit Description
CPVEIFAC: “Charge Pump Voltage Error Interrupt Flags Automatic Clear” enable bit.
6 1 = CPVEIF in the RSTSTAT register (Table 3.1) is automatically cleared when the interrupt event is resolved.
0 = Automatic clearing of CPVEIF is disabled.
SEIFAC: “Supply Error Interrupt Flags Automatic Clear” enable bit.
5
1 = Supply error flags UVIF and OVIF in the RSTSTAT register are automatically cleared when the interrupt
event is resolved.
0 = Automatic clear of supply error flags is disabled.
WDTPMEN: Bit for enabling the WDT during SLEEP and STANDBY Modes.
4 1 = WDT is enabled and running in SLEEP and STANDBY Modes.
0 = WDT is disabled in SLEEP and STANDBY Modes.
OVDP: “Over-Voltage Drivers Protection” enable bit.
3 1 = Over-voltage event automatically disables all drivers (HB, HS, ECM).
0 = The drivers are enabled even if an over-voltage event is detected.
UVDP: “Under-Voltage Drivers Protection” bit.
2 1 = Under-voltage event automatically disables all drivers (HB, HS, ECM).
0 = The drivers are enabled even if an under-voltage event is detected.
STBY: STANDBY Mode enable bit.
1 1 = Enables the STANDBY Mode.
0 = The system stays in NORMAL Mode.
SLEEP: SLEEP Mode enable bit.
0 1 = Enables the SLEEP Mode.
0 = The system stays in NORMAL Mode.
© 2016 Integrated Device Technology, Inc.
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January 26, 2016