ZAMC4100 Datasheet, PDF (128/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
4.10.3. 32 Bit Timer Registers
The 32-bit timer registers are mapped into the system address space between 0x4000_1000 and 0x4000_13FF.
Unused addresses must not be accessed.
Table 4.17 Register [0x4000_1000] T32_CTRL
T32_CTRL
ADD:0x4000_1000
Bit
Name
Ext.
Int. Reset
Access Access Value
0
EN
R/W R/W
0
1
MODETC
R/W
R
0
2
MODESR
R/W
R
0
3
MODELE
R/W
R
0
4
MODEPN
R/W
R
0
5
OVERFLOW
R
31 : 6
---
R
R/W
0
---
0
Description
Enable bit for timer. This bit is cleared by hardware if an over-
flow occurs and the module is operating in single shot mode.
Select between timer and counter mode:
0: timer mode
1: counter mode
Select between reload and single shot mode:
0: reload mode; at overflow, reload value is copied into
counter register and counter continues
1: single shot mode; at overflow, reload value is copied into
counter register and counter stops
Select between level or edge sensitive trigger;
counter mode only:
0: trigger is used as level sensitive
1: trigger is used as edge sensitive
Selects between rising or falling edge active trigger
(MODELE = 1) or high or low level (MODELE = 0);
counter mode only
0: Trigger on falling edge/low level
1: Trigger on rising edge/high level
Overflow flag (strobe); set for a single cycle when counter
overflows. This bit also drives the interrupt line.
Unused; always read as 0.
© 2016 Integrated Device Technology, Inc.
128
January 26, 2016