ZAMC4100 Datasheet, PDF (105/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
4.2.1. Accessing Invalid Memory Location
A default slave replies with an error response if unused parts of the memory space are accessed. For more
details, refer to the “AMBA 3 AHB-Lite Protocol Specification” section of the ARM® CORTEX™-M0 Document Kit.
4.2.2. FLASH Memory
FLASH memory implements three regions (see Figure 4.1):
• INFO Contains READ-only parameter data set by manufacturing as well as memory protection
management.
• BOOT Optionally used by a bootloader. The size of this area is programmable.
• PROG Program code memory, up to 32KB.
Each FLASH memory region is built with several pages of 512 bytes each. Each page is built with 4 rows and
each row contains of 32 words (1 word = 32 bits). One flash page is the smallest block that can be erased.
As the FLASH memory has some dedicated timings for the control signals when erasing (all or part of) the FLASH
and when writing data to the FLASH, a flash controller is used to support all mandatory operations (READ,
WRITE, ERASE) to be performed on the different locations and to guarantee the correct timings for write and
erase operations. Additionally, it is checked if the different operations are allowed to be performed depending on
the memory protection scheme.
Figure 4.1 Structure of FLASH Memory and Page Details
32K
0x07FFF
1K
0x0
INFO
PROG
BOOT
MAIN
1 Page = 512 Byte
Row-1
Row-2
Row-3
Row-4
1 ROW = 32 WORDS
0x00E00 _{progStart [0x07]}
0x00000
31
1 WORD = 32Bits
0
1 WORD, ½ WORD and Byte Access
© 2016 Integrated Device Technology, Inc.
105
January 26, 2016