ZAMC4100 Datasheet, PDF (132/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
4.10.5. SW-LIN Registers
The registers of the SW-LIN module are mapped into the system address space between 0x4000_1800 and
0x4000_181F. Unused addresses must not be accessed.
Table 4.25 Register [0x4000_1800] Z1_LINCFG
Z1_LINCFG
ADD:0x4000_1800
Bit
Name
Ext.
Int. Reset
Access Access Value
Description
0
STOPRX
R/W
R
0 This bit is a strobe register to stop the receiver.
When writing 1 to this bit, the state machine of the data
reception unit is placed into its default state (RXEN and
RXACTIVE are cleared) and waits for a new sync strobe. This
can be used by software to reject incoming data after the PID
field has been evaluated as a non-used PID.
1
DISABLERX R / W
R
0 When set to 1, this bit completely disables the BREAK/SYNC
field detector, the RX data path, and the RX filter. It must be
set when the system clock will be switched off, when the clock
divider will be changed, when LIN will go to sleep but the
MCU will continue operation, or for debugging purposes.
2
FASTMODE R / W
R
0 This bit distinguishes between slow (0) and fast (1) mode.
In slow mode, the detected baud rate is between 1kBaud and
30kBaud.
In fast mode, the detected baud rate is up to 200KBaud for
CLKDIV values 0, 1, and 2 and up to 100KBaud for CLKDIV
value of 3 (see Table 4.5).
3
ENTOCNT R / W
R
0 This bit enables the timeout counter for bus inactivity. The LIN
protocol requires that the LIN controller must go to sleep when
either a SLEEP command was received or after more than 4s
of inactivity. If the overall system guarantees that LIN
communication is always stopped with a SLEEP command,
there is no need to activate the timeout counter.
4
RXEN
R
R/W
0 This bit reflects the status of the receiver.
It is set when a BREAK/SYNC field is detected and it is
cleared when software stops the receiver (STOPRX = 1) or
when a transmission is started.
5
RXACTIVE
R
R/W
0 This bit reflects the status of the receiver.
It is set when a START condition is detected on the bus
(falling edge of RXD line after synchronization). It is cleared
when the software stops the receiver (STOPRX = 1), when a
new sync strobe occurs, in the middle of a received STOP bit,
or when a transmission is started.
6
TXACTIVE
R
R/W
0 This bit reflects the status of the transmitter. It is set if data is
present in the TX buffer to be transmitted. It is cleared if a sync
strobe or a bus conflict (sending 1 but receiving 0) is detected,
if the transmitter is forced to 1 by protection logic (sending 0
but receiving 1), or when no more data to be transmitted is
present in the TX buffer at the end of an active transmission.
© 2016 Integrated Device Technology, Inc.
132
January 26, 2016