ZAMC4100 Datasheet, PDF (133/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
Z1_LINCFG
Bit
Name
31 : 7
---
ADD:0x4000_1800
Ext.
Int. Reset
Access Access Value
R
---
0
Description
Unused; always read as 0.
Table 4.26 Register [0x4000_1804] Z1_LINSTAT
Z1_LINSTAT
ADD:0x4000_1804
Bit
Name
Ext.
Int. ^Reset
Access Access _Value
Description
0
SYNCDET
RC
R/W
0 This bit is set by hardware when a BREAK/SYNC field has
been detected by the break-/sync-field detector. It is cleared
when software reads this register.
1
RXFULL
R
R/W
0 This bit is set by hardware when a received byte is placed into
the RX buffer. It is cleared when the software reads the data
out of the RX buffer (read from LINDATA;Table 4.27).
2
TXEMPTY
R
R/W
1 This bit is set when a byte to be transmitted is read out of the
TX buffer to be shifted out on the LIN bus. It is cleared when
the software puts a new byte into the TX buffer (write to
LINDATA).
3
CONFLICT
RC
R/W
0 This bit is set by hardware when it has detected a bus conflict
during an active transmission. This can only occur when
sending a 1 but receiving a 0. It is cleared when software
reads this register.
4
RXOVERFLOW RC
R/W
0 This bit is set by hardware if the receiver attempts to place a
received byte into the RX buffer while this buffer is already
full. The new received byte is rejected and lost. This bit is
cleared when software reads this register.
5
WRCOLL
RC
R/W
0 This bit is set by hardware if software tries to write a byte into
the TX buffer while this buffer is already full. The new written
byte is rejected. This bit is cleared when the software reads
this register.
6
TXOFF
RC
R/W
0 This bit is set by hardware if it is transmitting a 0 but receives
a 1. As 0 is the dominant level on the bus; this can only occur
due to hardware error or if the bus protection circuit has
disabled the output driver in the LIN PHY. This bit is cleared
when software reads this register.
7
INACTIVE
RC
R/W
o This bit is set when the timeout counter for inactivity has
expired. This bit is cleared when software reads this register.
© 2016 Integrated Device Technology, Inc.
133
January 26, 2016