ZAMC4100 Datasheet, PDF (130/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
4.10.4. SPI Registers
The registers of the SPI module are mapped into the system address space between 0x4000_1820 and
0x4000_1BFF. Unused addresses must not be accessed.
Table 4.21 Register [0x4000_1820] Z1_SPICFG
Z1_SPICFG
ADD:0x4000_1820
Bit
Name
Ext.
Int. Reset
Access Access Value
0 RXOVERFLOW R / W
R
0
1
RXFULL
R/W
R
0
2
TXEMPTY
R/W
R
0
3
WRCOLL
R/W
R
0
4
---
R
---
0
5
SAMPLEPOS
R/W
R
0
6
7
31 : 8
SSN
SPIEN
---
R/W R/W
1
R/W R/W
0
R
---
0
Description
When set to 1, the corresponding status bit is allowed to drive
the IRQ output.
When set to 1, the corresponding status bit is allowed to drive
the IRQ output.
When set to 1, the corresponding status bit is allowed to drive
the IRQ output.
When set to 1, the corresponding status bit is allowed to drive
the IRQ output.
Unused; always read as 0.
This bit selects whether data on MISO will be sampled at the
sampling edge (set to 0) or at shift edge (set to 1).
Note: Change this bit only when the module is disabled
(SPIEN = 0) or when no transfer is in progress.
This bit directly controls the SSN line.
Enable for SPI module.
Unused; always read as 0.
Table 4.22 Register [0x4000_1824] Z1_SPIDATA
Z1_SPIDATA
ADD:0x4000_1824
Bit
Name
Ext.
Int. Reset
Access Access Value
7:0
SPIDATA
R/W R/W
0
31 : 8
---
R
---
0
Description
When writing a byte to this register, the value is stored in the
TxBuffer. Additionally a WRITE access to this register clears
the TXEMPTY flag in the Z1_SPISTAT register (Table 4.24).
When reading this register, the contents of the RxBuffer is
returned. Additionally a READ access to this register clears
the RXFULL flag in Z1_SPISTAT.
Note: When writing to this register when TxBuffer is full, the
TxBuffer keeps its contents and the written byte is rejected.
This is signaled by the WRCOLL flag in Z1_SPISTAT.
Unused; always read as 0.
© 2016 Integrated Device Technology, Inc.
130
January 26, 2016