ZAMC4100 Datasheet, PDF (138/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
FC_IRQ_EN
Bit
Name
6
ENIRQ6
7
ENIRQ7
31 : 8
---
ADD:0x4000_0810
Ext.
Int. Reset
Access Access Value
R/W
R
0
R/W
R
0
R
---
0
Description
drive the interrupt line.
When set to 1, the status signal DATA2ERR is allowed to
drive the interrupt line.
When set to 1, the status signal PROG1ERR in the
FC_STAT_PROG register (Table 4.37) is allowed to drive the
interrupt line.
Unused; always read as 0.
Table 4.36 Register [0x4000_0814] FC_STAT_CORE
FC_STAT_CORE
ADD:0x4000_0814
Bit
Name
Ext.
Int. Reset
Access Access Value
Description ¹⁾
0
CMDRDY
RC
R/W
0
This bit is set when a command execution has finished; it is
cleared when this register is read.
1
INVALIDCMD
RC
R/W
0
This bit is set when an invalid command was executed; it is
cleared when this register is read.
2
INVALIDAREA
RC
R/W
0
This bit is set when a command is executed targeting a
protected area; e.g., performing ERASE_MAINPAGE_CMD
to program space when flash is locked; it is cleared when this
register is read.
3
UNLOCKFAIL
RC
R/W
0
This bit is set when the UNLOCK_CMD fails; it is cleared
when this register is read.
4
COREACTIVE
R
R/W
0
This bit reflects the status of the core state machine; when
set core is active.
5
ALLOWKEY
R
R/W
0
When this bit is set but FLASH is locked, the
ERASE_KEY_CMD is allowed to be performed.
6
ALLOWBOOT
R
R/W
0
When this bit is set but FLASH is locked, the WRITE_CMD is
allowed to be performed on the boot space.
7
ALLOWPROG
R
R/W
0
When set but FLASH is locked, the WRITE_CMD is allowed
to be performed on the program space.
8
CLRALLOW
W1C
R
0
Writing 1 to this bit clears ALLOWKEY, ALLOWBOOT, and
ALLOWPROG flags.
31 : 9
---
R
---
0
Unused; always read as 0.
1) For related FLASH controller command codes, see Table 4.34.
© 2016 Integrated Device Technology, Inc.
138
January 26, 2016