ZAMC4100 Datasheet, PDF (38/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
3.3. Watchdog Timer (WDT)
The ZAMC4100 has a watchdog timer implemented in the SBC chip with the following features:
• MCU reset and system reset generation
• Running on the dedicated oscillator clock (125kHz)
• 8 programmable time-outs for MCU reset generation
• 4 settings for system reset generation
• Configuration register lock bit for avoiding unintentional configuration changes
• WDT clearing mechanism using bit toggling
• WDT reset status bit showing the reset event (MCU or system reset)
• Usage as a wake-up event during SLEEP and STANDBY Mode
3.3.1. WDT Structure and Operation Principals
The watchdog timer (WDT) has a dedicated free running oscillator (OSCL), which allows operation even when the
main oscillator has stopped (e.g., in SLEEP Mode). The WDT structure is shown in Figure 3.4.
Figure 3.4 ZAMC4100 Watchdog Timer
WDTIE
STBY
WDTIF
WDT time-base
Osc
125kHz
WDTEN
WDTPMEN
SLEEP
STBY
Divider
en clr
10ms
Postscaler
MCU reset
3
WDTCLR
MWDPOS[2:0]
SLEEP
STBY
Postscaler
System reset
2
SWDPOS[1:0]
STBY
wake-up
mcu_rst
sys_rst
SLEEP
wake-up
The WDT is configured and controlled via register WDTCONF (see Table 3.3). The WDT is enabled with bit
WDTEN = 1. Once enabled, it continuously generates 10ms periods that are counted by two post-scalers and two
time-out resets are generated:
1. Time-out for a MCU reset: after the configured time, the WDT resets the MCU.
2. Time-out for system reset: after the configured number of consecutive MCU resets, the WDT resets the
whole system (SBC and MCU chip).
© 2016 Integrated Device Technology, Inc.
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January 26, 2016