ZAMC4100 Datasheet, PDF (124/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
Table 4.7 Register [0x4000_0008] SYS_MEMINFO
SYS_MEMINFO
ADD: 0x4000_0008
Bit
Name
Ext.
Access
Int.
Access
Reset
Value
7 : 0 PROGSTART
R
R/W
0xFF
15 : 8 LOGSTART
R
R/W
0xFF
26 : 16 RAMSPLIT
R
R/W
0x7FF
27
---
R
31 : 28 PROTINFO
R
---
0
R/W
0xF
Description
This register represents the first page where the program
section inside the FLASH starts. This value is read from
FLASH during the power-up phase and is updated by
some flash commands.
Note: To determine the correct FLASH address offset,
seven "0" must be appended.
This register represents the first page where the log
section inside the FLASH starts. This value is read from
the FLASH during the power-up phase and is updated by
some FLASH commands.
Note: To determine the correct FLASH address offset,
seven "0" must be appended.
This register represents the first RAM word that is
accessible by JTAG although the memory is locked. This
value is read from FLASH during the power-up phase and
is updated by some FLASH commands.
Note: To determine the correct RAM address offset, two
"0" must be appended.
Unused; always read as 0.
This register represents the memory protection scheme.
This value is read from FLASH during the power-up
phase and is updated by some FLASH commands.
[0]: key-based lock
[1]: permanent lock
[3:2]: number of failed unlock attempts
Table 4.8 Register [0x4000_000C] SYS_RSTSTAT
SYS_RSTSTAT
ADD: 0x4000_000C
Bit
NAME
Ext.
Int. Reset
Access Access Value
Description
0
EXTRST
RC
---
1
This bit reflects if an external reset has occurred. It is cleared
when the register is read.
1
SYSRSTREQ
RC
W
0
This bit reflects if a reset forced by a system reset request
has occurred. It is cleared when the register is read.
2
LOCKUPRST
RC
W
0
This bit reflects if a reset was forced by a detected lockup
when this reset was enabled. It is cleared when the register is
read.
3
JTAGRST
RC
W
0
This bit reflects if a reset that was forced by a JTAG reset
request has occurred. It is cleared when the register is read.
6:4
---
R
---
0
Unused; always read as 0.
© 2016 Integrated Device Technology, Inc.
124
January 26, 2016