ZAMC4100 Datasheet, PDF (110/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
4.4. MCU INTERRUPTS
4.4.1. Interrupts Organization
Figure 4.4 shows the peripheral interrupts with the related control and status registers. Each peripheral has a
unique IRQ line that is attached to dedicated interrupt lines 0 to 5, which go to the nested vector interrupt
controller (NVIC) module within the ARM® CORTEX™-M0 processor. For more information about the NVIC, refer
to the NVIC chapter of the ARM® CORTEX™-M0 Document Kit.
Figure 4.4 MCU Interrupt Logic Organization
ECC
PROG: Double Bit Error
NMI
SBC
Interrupt
Controller
IRQN
CONTAINS IRQ EN BITS
FC-STAT-CORE
FC-IRQ-EN
Z1_LINSTAT
Z1_LINIRQEN
Z1_SPISTAT
Z1_SPICFG
TIMER MODULE
(Counter Overflow)
SBC
IRQEDGE
IRQEN
MCU
FLASH
Line 0
SW-LIN
SPI
Line 1
Line 2
NVIC
Interrupt
Controller
Line 3
32 BIT TIMER
Line 4
GPIO
Line 5
Peripherals
ARM® CORTEX™-M0 CORE
CORTEX™-M0
PROCESSOR
Note: The Systick has an NVIC number of -1 which is within the Cortex™-M0 core. For more details, refer to the
ARM® CORTEX™-M0 Document Kit.
© 2016 Integrated Device Technology, Inc.
110
January 26, 2016