ZAMC4100 Datasheet, PDF (71/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
3.10.4. PWM Initialization
This section describes the recommended PWM initialization flow which ensures no latency between the SPI driver
enable and driver’s output response. As an example, the initialization process using PWM control of the driver
HS3 is illustrated. In order to have pulse-width modulation at the HS3 pin, the MCU should execute the following
procedure (see Figure 3.17):
1) Enable PWM control for the HS3 driver by setting the HS3PWMEN bit of the PWMDREN register (see
Table 3.25).
2) Enable driver HS3 by setting the HS3EN bit of the HSDCTRL register (Table 3.20).
3) Configure the PWM frequency by writing to register PWMFCFG (Table 3.50).
4) Configure the PWM duty cycle by writing in register PWMDCFG (Table 3.50) a value greater than zero.
Until step 4 is executed, the driver’s output is disabled. After configuring the duty-cycle (in step 4), the PWM
module starts operating; i.e., it starts modulating the HS3 output.
In order to disable the PWM at the driver’s output, the MCU should execute the following (recommended)
procedure (see Figure 3.17):
1) Write zero in register PWMDCFG in order to stop PWM generation. As shown in Figure 3.17, the PWM
stops after the end of the current period. The value in the PWMFCFG register can be left unchanged.
2) Disable the driver by clearing bit HS3EN of register HSDCTRL.
3) Disable the PWM for driver HS3 by clearing the HS3PWMEN bit. If step 2 is omitted (bit HS3EN still set),
the execution of this step will enable the driver.
Figure 3.17 Recommended PWM Initialization Procedure with HS3 as an Example
HS3PWMEN 1
3
HS3EN
2
2
PWMFCFG
0x00 3
0x1C (example value)
PWMDCFG
PWM signal
0x00
4
0x3A (example value)
PWM start
1
0x00
PWM stop
HS3
The initialization flow explained above should be considered as a recommendation for ensuring that the
application has no latency between setting the enable bits and driver’s output reaction.
The ZAMC4100 has internal synchronization logic that prevents glitches at each driver’s output in case the
driver’s enable bit is set when the generation of PWM signal is already running. In this event, the driver enable will
be synchronized with the PWM signal, which will cause a latency of one PWM period (worst case). See Figure
3.18 for an illustration of the synchronization effect.
© 2016 Integrated Device Technology, Inc.
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January 26, 2016