ZAMC4100 Datasheet, PDF (24/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
1.3.3. SPI Bus Timing
Refer to Figure 1.2 and Table 1.16 for the definitions of the SPI timing parameters.
Table 1.16 ZAMC4100 SPI Bus Timing Parameters
Parameter
SPI clock period ¹⁾
Symbol
tCLK
Min.
0.3
Typ.
-
Max.
6.4
Unit
µs
SPI pulse width
Chip-select setup time ²⁾
Chip-select hold time ²⁾
tP
tCSNSU
tCSNHD
40% tCLK
50% tCLK
60% tCLK
µs
1.0
-
-
µs
1.0
-
-
µs
SPI access time
tACC
1.0
2.0
-
µs
1) The maximum tCLK value is determined by the maximum value that can be programmed in MCU register Z1_SPICLKCFG[7:2] (see Table 4.23).
2) The parameters tCSNSU and tCSNHD require at least 3 OSCH clock cycles. When oscillator OSCH is not trimmed, it runs at a lower frequency.
Figure 1.2 SPI Communication Timing Diagram
CSN
tCSNSU
tCLK
tP
SPI_CLK
MOSI
765
10765
tCSNHD tACC
10
MISO
765
10765
10
CMD/SSB
R/W DATA
76
76
© 2016 Integrated Device Technology, Inc.
24
January 26, 2016