ZAMC4100 Datasheet, PDF (104/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
4.2. Memory Organization
The MCU contains two memory blocks: FLASH (program) memory and SRAM (data) memory. Together with the
peripheral and system registers, their addresses are mapped as shown in Table 4.1. By default, the flash is
mirrored to address 0x0. Software can change this and mirror the SRAM to address 0x0 instead by writing to the
register field MEMSWAP in register SYS_MEMPORTCFG (see Table 4.6).
Table 4.1 MCU Memory Map
Address
Description
0xFFFF_FFFF
0xE010_0000
0xE00F_FFFF
0xE000_0000
0xDFFF_FFFF
0x4000_1C00
0x4000_1BFF
0x4000_1800
0x4000_17FF
0x4000_1400
0x4000_13FF
0x4000_1000
0x4000_0FFF
0x4000_0C00
0x4000_0BFF
0x4000_0800
0x4000_07FF
0x4000_0400
0x4000_03FF
0x4000_0000
0x3FFF_FFFF
0x2000_0800
0x2000_07FF
0x2000_0000
0x1FFF_FFFF
0x1000_8000
0x1000_7FFF
0x1000_0000
0x0FFF_FFFF
0x0000_0000
Reserved
Private Peripheral Bus; see the ARM® CORTEX™-M0 documentation for details
Reserved
(SPI, SW-LIN)
GPIO
32-Bit Timer
FLASH Info Page
FLASH Controller
Reserved
System Management Unit
Reserved
SRAM Bank 2KB
Reserved
FLASH Bank 32KB
Reserved
© 2016 Integrated Device Technology, Inc.
104
January 26, 2016