ZAMC4100 Datasheet, PDF (106/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
4.2.2.1. FLASH Single Bits Error Correction (ECC)
Each word is protected by ECC logic with a hamming distance of 4, which enables the system to correct a single
bit error and to detect two-bit errors within a word. The correct ECC code bits are automatically appended on
each WRITE access to the FLASH. When a single error within a word is detected during a READ access, it is
automatically corrected.
The occurrence of bit errors is signaled via dedicated status bits in registers FC_STAT_DATA (Table 4.38) and
FC_STAT_PROG (Table 4.37) inside the FLASH controller. The status bits distinguish between an erased
FLASH word (PROGALL1 flag), the detection and correction of a single-bit error (PROG1ERR flag), and the
detection of more than one bit error (PROG2ERR flag). The condition of more than one bit error is not correctable.
The two status register sets are distinguished by the type of FLASH access:
FC_STAT_PROG status bits are used when errors occur during an instruction fetch
• An instruction fetch to an erased memory location (PROGALL1 flag set) or the detection of more than one
bit error within a word will also assert a non-maskable interrupt (NMI) as the program is corrupted.
• The detection and correction of a single-bit error within a word is signaled via a normal interrupt (ARM®
interrupt line 0).
FC_STAT_DATA status bits are used when errors occur during a load operation
• Loads from an erased memory location as well as the detection (and correction) of errors within a word
are signaled via a normal interrupt (ARM® interrupt line 0).
4.2.2.2. FLASH Main Area
The MAIN area of the FLASH is physically located within the address range 0x1000_0000 to 0x1000_7FFF. It can
also be mirrored to address 0x0000_0000 by clearing the MEMSWAP bit in the SYS_MEMPORTCFG register
(see Table 4.6), which is a default setting.
The FLASH MAIN area is split into two sections: BOOT and PROG. Each section is built with multiple FLASH
blocks of 512 bytes. The BOOT and PROG sections must contain at least one FLASH block. This partition is only
needed for writes when memory protection is active and also for some erase commands.
The MAIN area can be READ with byte, half-word and word size. It can always be read by the ARM® processor
but reads via the JTAG interface are blocked when memory protection is active. The different sections have no
influence on READ accesses.
4.2.2.3. FLASH Controller
The flash controller handles all accesses to the different flash locations (INFO pages; MAIN area). It provides
different types of commands for modifying the flash contents, guarantees all required timings for the different
accesses to the FLASH, and checks the ECC code.
The FLASH controller contains a set of registers that are needed for command execution (see Table 4.33) and
observing their status. These registers are also used to enable the different interrupt sources to drive the interrupt
line. Additionally, there are two non-maskable interrupt sources that are connected to the NMI of the ARM® core.
Information for FLASH controller registers is given in section 4.10.6, and FLASH command timing is defined in
Table 1.18.
© 2016 Integrated Device Technology, Inc.
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January 26, 2016