ZAMC4100 Datasheet, PDF (112/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
4.5.3. GPIO Output Mode
Assigned bits in the GPIO_DIR register must be set for output operation for a specific GPIO pin (bit numbers
correspond to GPIO numbers). The value can be written into the GPIO_OUT register, which defines the GPIO
output level. If a single GPIO bit is to be modified, a more direct way to configure the bit is via the GPIO_SETCLR
register (see Table 4.12), which can be used instead of performing the read-modify-write operation.
Corresponding bits in the SETOUT[7:0] bit field are for setting the bit to 1 and corresponding bits in the
CLROUT[23:16] bit field are for clearing the bit.
Note: Write the initial value to the GPIO_OUT register before defining GPIO_DIR for the output.
4.5.4. GPIO as Timer Trigger Operation
Each GPIO pin can be used as an external trigger source for the 32-bit timer (see section 4.6.1). To enable the
trigger functionality, the GPIO pin must be configured as an input and the trigger functionality must be enabled via
the GPIO_TRIGEN register (Table 4.14).
4.5.5. GPIO Interrupt Functionality
Each GPIO pin can be used as an external, edge-sensitive interrupt source. To enable the interrupt functionality,
the GPIO pin must be configured as an input and the interrupt functionality must be enabled via register
GPIO_IRQEN (Table 4.14). Additionally, the GPIO_IRQEDGE register (Table 4.15) can be used to select whether
a rising or falling edge on the GPIO pin activates the interrupt.
All GPIO pins enabled as an external interrupt source drive a single interrupt line connected to the ARM®
interrupt 5. The user can determine which GPIO pin caused the interrupt by reading register GPIO_IRQSTAT
(Table 4.13). All interrupt status bits are cleared when reading register GPIO_IRQSTAT.
Note: As the synchronization flip-flops are only continuously clocked when the trigger or interrupt functionality is
enabled for the corresponding GPIO pin, it is possible that an unwanted interrupt occurs when enabling the
interrupt functionality. To avoid this, the following sequence must be guaranteed by software:
• Enable the GPIO trigger functionality and select the desired interrupt edge to be used.
• Enable the GPIO interrupt functionality at least three cycles after enabling as a trigger.
• Disable the GPIO trigger functionality.
4.5.6. GPIO Registers
Refer to section 4.10.2 for GPIO register details.
4.6. 32-Bit TIMER Module
The timer provides event-counting on the rising clock edge with a 32-bit resolution. When enabled (EN bit = 1 in
register T32_CTRL; see Table 4.17), the timer counts clock events in timer mode or counts events from a
selectable external trigger signal in counter mode as described in the next two sections. The external trigger can
be configured to operate on rising/falling edges or on a low/high level via the MODEPN and MODELE bits.
Additionally, the MODESR bit can be used to select whether the timer/counter stops when it overflows or
continues its operation.
© 2016 Integrated Device Technology, Inc.
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January 26, 2016