ZAMC4100 Datasheet, PDF(89/155 Page) Integrated Device Technology

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ZAMC4100 Datasheet, PDF (89/155 Pages) Integrated Device Technology – Actuator and Motor Controller

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ZAMC4100 Datasheet

Single ADC Conversion and SPI Pipeline Concept

The MCU starts a single ADC conversion by setting bit SCNV=1. When the conversion finishes, bit SCNV is

automatically cleared and the interrupt flag ADCRDYIF is set.

Since the SCNV and INPSEL bits share a register (ADCCTRL), the MCU starts a single conversion on only the

selected channel with one SPI WRITE access. Using the pipelined SPI WRITE/READ feature of the ZAMC4100

SBC, the MCU can pipeline the channelâs measurement and results monitoring. Figure 3.23 shows an example

for SPI communication when the MCU is measuring the current of the high-side drivers. See Table 3.50 for details

for the SPIDPRT register.

Figure 3.23 Pipelined Measurement and Results Reading for the Driver Current

MCU

SPI Bus: Pipelining ADC Conversion and Result Read

CMD = ADCCTRL write SCNV = 1, INPSEL = HS1 CMD = ADCCTRL write SCNV = 1, INPSEL = HS2 CMD = ADCCTRL write SCNV = 1, INPSEL = HS3

SBC

SSB

ADCRESH

SSB Ã CNVRDYIF

ADCRESH = I(HS1)

SSB Ã CNVRDYIF

ADCRESH = I(HS2)

Settings:

Result formatting: truncated 8-bit result

ADC Continuous Conversion

With the CCNV bit set, the ADC operates in continuous conversion mode at the sampling rate determined by the

ADCSR[2:0] bits. After each conversion with formatted data in the results register, the ADC generates the

interrupt flag ADCRDYIF (Table 3.39). The CCNVMD bit provides two options affecting the way the result register

is handled by the MCU:

Bit CCNVMD = 0

Bit CCNVMD = 1

The ADC continuous conversion is running and the results registers ADCRESH and

ADCRESL (Table 3.50) contain the latest conversion value. If the MCU does not read the

value, it is overwritten with the next one.

When the result is available, the ADC continuous conversion is halted until the MCU reads

the result value. Reading the conversion result clears the ADCRDYIF flag and the ADC

automatically continues with the next conversion. This mode allows the MCU to control the

ADC sample rate by controlling the time between two SPI READ accesses.

Note: Before enabling continuous conversion with CCNVMD = 1, the MCU should clear the ADCRDYIF bit (by

reading the result from previous conversions) in order to start the new ADC conversion.

3.12.8. ADC Result Formatting Options

While the SPI bus only handles 8-bit data transfers, the ADC result of 10 bits is split into two registers: ADCRESH

and ADCRESL. Prior to this, the ADC digitized data are formatted in accordance with the settings for the bits

RESJSTF and RESSIGN of register ADCCONF (Table 3.37). Bit RESJSTF configures left or right result

justification as explained in the following sections.

January 26, 2016

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