ZAMC4100 Datasheet, PDF (88/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
3.12.6. ADC Sample Rate
The ADC sampling rate is calculated as the maximum sampling rate (250Ksps) divided by the value configured in
bits ADCSR[2:0] of register ADCCONF (Table 3.37). Table 3.41 gives the definitions of the ADCSR[2:0] bits. t_CCNV
is the ADC continuous conversion phase. For more information on this and other ADC timing parameters, refer to
section 1.3.2.
The time between two consecutive conversion results is calculated as the sum of the following:
• ADC sample time (see Table 1.15 and Figure 1.1): configurable parameter (via ADCSR[2:0] bits) for all
modes except the external temperature conversion for which it is fixed.
• ADC conversion time (see Table 1.15 and Figure 1.1): fixed parameter which depends only on the OSCH
clock accuracy.
• ADC idle time (see Table 1.15 and Figure 1.1): configurable parameter (via ADCSR[2:0] bits) which
determines the sample rate for the external temperature conversion.
Each ADC start conversion command (single or continuous) counts a 10µs period needed for proper settling of
the ADC input stage.
Table 3.41 ADC Sample-Rate Configuration
ADCSR[2:0]
Sample Rate ^{1), 2)}
tCCNV
000
SRmax
001
SRmax/2
010
SRmax/4
011
SRmax/8
4µs
8µs
16µs
32µs
100
SRmax/16
101
SRmax/32
110
SRmax/64
111
SRmax/128
64µs
128µs
256µs
512µs
1) The value of SRmax is specified in Table 1.15. The tCCNV (ADCSR=0) is calculated based on 1/SRmax =
1/250Ksps.
2) The maximum possible sample rate for the external temperature conversion is SRMAX/8. For
ADCSR[2:0] values in the range from 000 to 011, the external temperature conversion is running at
SRmax/8
3.12.7. ADC Single and Continuous Conversion
Single or continuous conversion operation is defined by the SCNV and CCNV bits respectively, in the ADCCTRL
register (Table 3.34). If this bit is set, the ADC will automatically start the conversion process. It sets the interrupt
flag ADCRDYIF in the ADCSTAT register (Table 3.39) when the conversion process is completed with the results
(after the formatting process) stored in registers ADCRESH and ADCRESL (Table 3.50). This interrupt flag is
cleared after reading the result registers. If both of the SCNV and CCNV bits are set, the ADC operates in
continuous conversion mode.
The output of the ADC goes to the results formatting block, where there are four options for result representation
as detailed in section 3.12.8.
© 2016 Integrated Device Technology, Inc.
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January 26, 2016