ZAMC4100 Datasheet, PDF (136/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
4.10.6. FLASH Memory Registers
The registers of the FLASH controller are mapped into the system address space between 0x4000_0800 and
0x4000_0BFF. Unused addresses must not be accessed. Read accesses to registers are always performed even
if a command is executed or a direct WRITE is active. Write accesses to the registers are postponed until the
active command/direct-write access has finished.
Table 4.31 Register [0x4000_0800] FC_RAM_ADDR
FC_RAM_ADDR
ADD:0x4000_0800
Bit
Name
Ext.
Int. Reset
Access Access Value
Description
10 : 0
ADDRRAM R / W
R/W
0
RAM word address where data to be written into flash is
located (first address); hardware increments this address
when more than one word has to be written.
Note: The last two address digits of the RAM are not included
as they are always 0. For programming, the RAM address
needs to be shifted right by two bits.
31 : 11
---
R
---
0
Unused; always read as 0.
Table 4.32 Register [0x4000_0804] FC_FLASH_ADDR
FC_FLASH_ADDR
ADD:0x4000_0804
Bit
Name
Ext.
Int. Reset
Access Access Value
Description
14 : 0
FLASHADD
R/W
R
R
0
FLASH word address (first address) where data is to be
written; also used as the pointer to a page to be erased.
Note: the last two address digits of the FLASH are not
included as they are always 0. For programming, the FLASH
address needs to be shifted right by nine bits.
31 : 15
---
R
---
0
Unused; always read as 0.
Table 4.33 Register [0x4000_080C] FC_EXE_CMD
FC_EXE_CMD
ADD:0x4000_080C
Bit
Name
Ext.
Int. Reset
Access Access Value
0
EXECMD
R/W
R
0
31 : 1
---
R
---
0
Description
Writing 1 to this bit starts the execution of the configured
command; always read as 0.
Unused; always read as 0.
© 2016 Integrated Device Technology, Inc.
136
January 26, 2016