ZAMC4100 Datasheet, PDF (35/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
Figure 3.2 ZAMC4100 Clock Sources
OSCH ^20MHz
OSCL ^125kHz
MCU Clock
5 ^4MHz _{0 SBC Clock}
1
SLEEP
WDT
LIN
Wake-up
OSCL Failure
Detection
OSCLEIF
OSCL Failure Detection
In order to increase the system robustness, the ZAMC4100 features a mechanism for failure detection in the
OSCL clock generation. This ensures that the MCU is alerted by an interrupt in the event of the watchdog timer
not functioning (caused by an OSCL clock stop).
The OSCL clock is observed by dedicated circuitry running on the OSCH clock. If for any reason the OSCL clock
stops, then an OSCL failure event is detected, captured in the flag OSCLEIF (see Table 3.1), and propagated as
an interrupt to the MCU. Then the MCU firmware can determine whether to perform any failure protection actions
(for example, a failure report to the electronic control unit ECU via LIN) or to continue with the regular firmware
execution.
Note: In SLEEP Mode, the OSCL failure detection is disabled because the OSCH clock is stopped, i.e. no OSCL
clock observation is possible.
3.2.2. Reset Sources
The ZAMC4100 system has three resets all generated within the SBC chip. Each reset source has its own flag bit.
The MCU can distinguish between the different resets by reading the contents of register RSTSTAT (Table 3.1
and Table 3.2). The flags of the RSTSTAT register are cleared by writing a ‘1’ in the corresponding bit of the
RSTSTAT register.
© 2016 Integrated Device Technology, Inc.
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January 26, 2016