ZAMC4100 Datasheet, PDF (139/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
Table 4.37 Register [0x4000_0818] FC_STAT_PROG
FC_STAT_PROG
ADD:0x4000_0818
Bit
Name
Ext.
Int. Reset
Access Access Value
Description
17 : 0 ADDRPROG
R
R/W
0
This register contains the address of the instruction fetch
error that caused the first of the three flags below to be set;
the highest bit is used to distinguish between MAIN (0) and
INFO (1) area.
28 : 18
---
R
---
0
Unused; always read as 0.
29
PROGALL1
RC
R/W
0
This bit is set when an instruction fetch occurs to an erased
memory address; it is cleared when this register is read.
30
PROG1ERR
RC
R/W
0
This bit is set when a correctable error occurs during an
instruction fetch; it is cleared when this register is read.
31
PROG2ERR
RC
R/W
0
This bit is set when an un-correctable error occurs during an
instruction fetch; it is cleared when this register is read.
Table 4.38 Register [0x4000_081C] FC_STAT_DATA
FC_STAT_DATA
ADD:0x4000_081C
Bit
Name
Ext.
Int. Reset
Access Access Value
Description
17 : 0 ADDRDATA
R
R/W
0
This register contains the address of the read error which
caused the first of the three flags below to be set; the highest
bit is used to distinguish between MAIN (0) and INFO (1)
area.
28 : 18
---
R
---
0
Unused; always read as 0.
29
DATAALL1
RC
R/W
0
This bit is set when a READ is performed to an erased
memory address; it is cleared when this register is read.
30
DATA1ERR
RC
R/W
0
This bit is set when a correctable error occurs during a read;
it is cleared when this register is read.
31
DATA2ERR
RC
R/W
0
This bit is set when an un-correctable error occurs during a
READ; it is cleared when this register is read.
© 2016 Integrated Device Technology, Inc.
139
January 26, 2016