ZAMC4100 Datasheet, PDF (57/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
If the data is successfully shifted into the SBC, the WRITE command is executed on the rising edge of CSN. This
allows the MCU to control precisely the moment when the data is written. For example, the drivers are enabled by
writing in their control register (see sections 3.8, 3.9, or 3.11) and in this case the CSN rising edge marks the
beginning of the motor operation.
3.7.3. SPI Pipelined Write/Read Access
In order to provide bidirectional data transfer, the SBC SPI slave provides functionality for performing a register
data READ while the WRITE frame is transferred. This functionality is implemented as automatic indirect
addressing of the SBC registers using the SPIDPTR register (Table 3.50) as the data pointer.
Register SPIDPTR points to the address of the register from which content will be automatically shifted out while
the SBC receives the data WRITE byte. This feature allows pipelining of the ADC conversion and the data WRITE
(see section 3.12.7).
3.7.4. SPI Read Access
To read data from SBC registers, the MCU sends a frame as shown in Figure 3.10–B.
1) Command byte (CMD) with the R/ W bit = 1, the 5-bit address of the register that is going to be read, and
the B bit with a value depending on the READ access type:
a. Single data read: B = 0
b. Burst data read: B = 1
2) Data byte: The MCU sends dummy data bits (keep as 0) while the SBC shifts out the contents of the
register pointed to by the address value in the command field.
The SPI read access allows the MCU to read more than one data byte. The SBC shifts out data as long as the
CSN line is low and the SPI clock is running. If bit B = 0, the SBC shifts out all data from only one address, i.e.
continuous reading of a single address (Figure 3.11-A). If bit B = 1, the SBC shifts out multiple consecutive data
bytes and increments the address after sending each byte (Figure 3.11-B). In the case of a one-byte READ, the B
bit value is “don’t care.”
Figure 3.11 SPI Single or Burst Access
A) Single Address SPI READ
CSN
MOSI
MISO
7
0
1 Address[4:0] 0
7
0
SSB
7
0
7
0
RD DATA(Addr)
7
0
7
0
RD DATA (Addr)
B) Burst SPI READ
CSN
MOSI
MISO
7
0
1 Address[4:0] 1
7
0
SSB
7
07
0
7
07
0
RD DATA(Addr)
RD DATA (Addr+1)
© 2016 Integrated Device Technology, Inc.
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January 26, 2016