ZAMC4100 Datasheet, PDF (123/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
4.10. MCU Registers Description
4.10.1. System Registers
The SMU registers are mapped into the system address space between 0x4000_0000 and 0x4000_03FF.
Unused addresses must not be accessed.
Table 4.5 Register [0x4000_0000] SYS_CLKCFG
SYS_CLKCFG
ADD: 0x4000_0000
Bit
Name
Ext.
Access
Int.
Access
Reset
Value
1:0
CLKDIV
R/W
R
0
6:2
---
R
---
0
7
---
R/W
R
0
31 : 8
---
R
---
0
Description
Clock divider value:
0: Incoming clock is divided by 1
1: Incoming clock is divided by 2
2: Incoming clock is divided by 4
3: Incoming clock is divided by 8
Unused; always read as 0.
Reserved.*
Unused; always read as 0.
Table 4.6 Register [0x4000_0004] SYS_MEMPORTCFG
SYS_MEMPORTCFG
ADD: 0x4000_0004
Bit
Name
Ext.
Access
Int.
Access
Reset
Value
7:0
PPNOD
R/W
R
0
15 : 8
N/A
N/A
N/A
0
17 : 16
N/A
N/A
N/A
0
20 : 18
N/A
N/A
N/A
0
23 : 21
N/A
N/A
N/A
0
29 : 24
---
R
---
0
30
LINTEST
R/W
R
0
31
MEMSWAP
R/W
R
0
Description
Output configuration bits.
It can be individually selected for each GPIO whether it
functions as an open-drain (set to 0) or as a push-pull
(set to 1).
Reserved.
Reserved, do not write to these bits.
Reserved, do not write to these bits.
Reserved, do not write to these bits.
Unused; always read as 0.
Configuration bit for LIN test. When set, RXD and TXD
lines are directly connected to the GPIO.
Memory swap bit. It can be selected whether the FLASH
MAIN area (set to 0) or the RAM (set to 1) will be
mirrored to system address 0x0.
© 2016 Integrated Device Technology, Inc.
123
January 26, 2016