ZAMC4100 Datasheet, PDF (69/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
Register PWMDREN contains local bits for enabling the PWM control for each half-bridge or high-side driver.
When all bits of PWMDREN are 0 (power-on-reset value), there is no driver using PWM control. In this case, the
PWM module is automatically disabled even if PWMDCFG is not 0.
3.10.2. PWM Signal Generation
The PWM module is enabled when at least one bit of the PWMDREN register is set (see section 3.10.3). In that
case, a signal with an adjustable frequency and duty-cycle is generated at the output of the PWM module (see
Figure 3.16).
Figure 3.16 PWM Output Signal
PWM
signal
PWMFCFG
PWMDCFG
PWMFCFG
PWMDCFG
The PWM frequency is configured via register PWMFCFG and is calculated using the formula:
PWMfreq
=
256
(Fosch / 80)
× [PWMFCFG
+
1]
,[Hz]
→
PWMFCFG ∈ [0:255]
The value of PWMFCFG determines the division ratio of the PWM prescaler (see Figure 3.15). The prescaler
determines the speed of incrementing the PWM counter value from 0 to 255, i.e. the duration of the PWM period.
Setting a minimum value for PWMFCFG provides a maximum PWM frequency of approximately 976Hz. Each
time the counter crosses zero, the following procedure is executed:
1) The comparator (PWM) output is set to high (if PWMDCFG = 0, the output is not set)
2) The PWM duty-cycle value from register PWMDCFG is latched to the shadow register (see Figure 3.15).
The PWM output stays high as long as the counter value is less than the value configured in register PWMDCFG.
When counter’s value matches the value of PWMDCFG, the comparator (PWM) output is cleared. This is the end
of the PWM duty cycle. The PWM duty cycle is calculated using the following formula:
PWMdc = ^[PWMDCFG] × 100,[%] → PWMDCFG∈[0:255]
256
A duty-cycle of 50% is achieved by writing the value 128_DEC in register PWMDCFG. Writing 0 to PWMDCFG
produces a continuous low level at the output of PWM module. The maximum PWMDCFG value 255_DEC produces
a duty-cycle of 99.6%.
Note: In order to have a continuously enabled driver (i.e. duty-cycle of 100%), the MCU should clear the
corresponding PWM enable of register PWMDREN.
© 2016 Integrated Device Technology, Inc.
69
January 26, 2016