ZAMC4100 Datasheet, PDF (54/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
Bit Description
HSOCIF: High-side driver over-current global interrupt flag.
1 = An over-current event has been detected in one or more high-side drivers. To determine the specific over-current
2
source, the MCU should read the HSxOCIF bits in the HSDSTAT register.
0 = Half-bridge driver over-current event was not detected.
Note: The HSOCIF interrupt flag cannot be directly cleared. In order to clear HSOCIF, the MCU should clear
HSxOCIF flags of register HSDSTAT (Table 3.22).
ECMOCIF: Over-current interrupt flag for the ECM driver. This bit is physically implemented in register ECMDIAG
and mapped to the IRQSTAT.
1 1 = An over-current event has been detected at the ECM output and the driver has been disabled.
0 = There is no over-current at the ECM output.
Note: The ECMOCIF interrupt flag can be cleared in the ECMDIAG register (Table 3.29).
LINIF: LIN PHY global interrupt flag.
1 = LIN PHY interrupt has occurred. There was a LIN wake-up, dominant time-out, or LIN short detected.
0 _{0 = LIN PHY interrupt did not occur.}
Note: The LINIF interrupt flag cannot be directly cleared. In order to clear LINIF, the MCU should clear the correlated
LINWUIF, LINDTOIF, or LINSHIF flags of the LINSTAT register (Table 3.48).
3.7. Serial Peripheral Interface (SPI) Bus Interface
The ZAMC4100 features an integrated Serial Peripheral Interface (SPI) that connects between the MCU and
SBC. It operates as a synchronous serial interface performing full-duplex data exchange driven by the clock
generated by the MCU. In the MCU, the SPI circuit block operates in MASTER mode and controls the SBC
peripherals (drivers, ADC, LIN).
SPI Features:
• Byte-wise frame structure
• 8-bit data read/write access
• Clock polarity = 1 (clock idle = 1, falling edge first)
• Clock phase = 1
§ Data shift-out on falling edge
§ Data capturing on rising edge
• Low-active chip select (CSN)
• 8-bit SBC status automatically shifted out to MCU
• Pipelined write/read access for fastest SBC to MCU interaction
• Data write frame validation feature
• The SPI read starts at the specified address, and if the clock continues, it continues shifting out the data
from next address
• Continuous data read mode (of a single address) without intermediate CSN toggling
§ Useful for ADC result data access
© 2016 Integrated Device Technology, Inc.
54
January 26, 2016