ZAMC4100 Datasheet, PDF (108/155 Pages) Integrated Device Technology – Actuator and Motor Controller

ZAMC4100 Datasheet
The entire RAM is always accessible by the ARM® processor, but there are restrictions for RAM access via the
JTAG interface. From the perspective of the JTAG interface, the RAM is split into two sections with a boundary
configurable via the RAMSPLIT bit field in the SYS_MEMINFO register (see Table 4.7).
Figure 4.2 Example of RAMSPLIT Address Configuration
0x007FF
0x007FF
0x0063F
0x0063B
SRAM
0x0063C ^{Programmed RAMSPLIT address}
0x00638 ^{[0x18F] (0x0063C>>2)}
0x00007
0x00003
4 Byte = 1 Word
0x00004
0x00000
The RAMSPLIT address is word-aligned and stored in the FLASH. The upper section starting with address
RAMSPLIT can always be accessed via JTAG. The lower section can only be accessed via JTAG when no
memory protection is active. The stack used by software must be placed into the lower section to avoid
unauthorized access, which could result in potentially damaging changes.
Notes:
1. Always place the software stack into the lower section of the RAM. The lower section ends one word
address before the address RAMSPLIT.
2. The RAMSPLIT address can always be determined from register SYS_MEMINFO (see Table 4.7). The
last two address bits are not included in the read value as they are always 0.
4.3. MCU Clock and Reset Sources
The RESET and clock operation are managed by the SBC as detailed in section 3.2. The main clock frequency is
set to 20MHz for the MCU core.
As shown in Figure 4.3, the MCU_CLK from the SBC go to the clock divider with 1:1 as the default divider. The
CLKDIV bit field in the SYS_CLKCFG register (Table 4.5) can be configured for other settings for the divider so
that the system runs at 20MHz, 10MHz, 5MHz, or 2.5MHz. It is not advisable to change the clock division setting
during any of these operations:
• FLASH programming
• LIN operations, unless the LIN module is put into the safe state, which is achieved by setting the
STOPRX bit and clearing the ENTOCNT bit in the Z1_LINCFG register (Table 4.25).
• Active operations associated with the 10msec reference of the SYST_CALIB register of the ARM® core.
This must be disabled before making adjustments for the clock division.
© 2016 Integrated Device Technology, Inc.
108
January 26, 2016