MB86290A Datasheet, PDF (98/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

LCO (displayList Count)
Register address ^{HostBaseAddress + 44h}
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
R0
0
LCO
RW
Don’t care
This register sets the DisplayList. transfer word count. When 1 is set, 1-word
data is transferred. When 0 is set, it is considered to be the maximum
number and 16M (16,777,216) words of data are transferred. The contents
set at this register do not change until another value is set.
LREQ (displayList transfer REQuest)
HostBaseAddress + 48h
Register address
Bit #
7
6
Bit field name
R/W
Default
5
4
3
Reserved
R0
0
2
1
0
LREQ
RW1
0
This register triggers DisplayList transfer from the Graphics Memory.
Transfer is started by setting LREQ to 1. DisplayList. The DisplayList is
transferred from the Graphics Memory to the internal display list FIFO.
Access to the display list FIFO by the CPU or DMA is prohibited while this
transfer is in progress.
7.1.2 Graphics Memory Interface Registers
MMR (Memory I/F Mode Register)
HostBaseAddress + FFFCh
Register address
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserve
W0
RX
00
Don’t care
TRRD
RW
11
TRC
RW
1001
TRP TRAS TRCD LOWD
RW
RW
RW RW
11
110
11
10
RTS
RW
0111
RAW ASW
RW ^RW
10 1
CL
RW
011
This register controls the graphics memory interface mode setting. An
appropriate value must be set at this register after reset (even if the default
value is used). This register is not initialized by a software reset.
Bits 2-0
CL (CAS Latency)
Set CAS latency cycles. Set same value at mode register of SDRAM.
011
CL3
010
CL2
Others
Prohibited
98