MB86290A Datasheet, PDF (159/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

8.1.10 SH3/4 Dual-address DMA Transfer End Timing
For the MB86290A, the read/write operation is performed according to the
SRAM protocol.
BCLKIN
DREQ
DRACK
A[24:2]
D[31:0]
Source address
Read
Destination address
Write
DTACK
Fig. 8.10 SH3/4 Dual-address DMA Transfer End Timing
DREQ is negated three cycles after DRACK is written as the last data.
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