MB86290A Datasheet, PDF (164/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

8.2.4 Timing of Write Access to Different Row Addresses
MCLKO
MRAS
TRAS
MCAS
MWE
MA
TRCD
ROW
COL
TRP
TRCD
ROW
COL
MD
DQM
ROW: Row Address
COL: Column Address
DATA: READ DATA
DATA
TRAS: RAS Active Time
TRCD: RAS to CAS Delay Time
TRP: RAS Precharge Time
DATA
Fig. 8.2.4 Timing of Write Access to Different Row Addresses
This timing diagram shows that different row addresses of SDRAM are write-
accessed from the MB86290A. An SDRAM page boundary is located between
the address to be written to first and the address to be written to next.
Consequently, the Precharge command is issued at the timing that meets the
TRAS condition, and then after TRP has elapsed, the ACTV command is
reissued and the Read command is issued.
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