MB86290A Datasheet, PDF (55/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

5.6.3 External Synchronization
Display scan can also be synchronized to external HSYNC/VSYNC signals.
When the external synchronization mode is set at the register, MB86290A
starts sampling the HSYNC signal input and displays the graphics output
synchronized to the external video signals. Either the internal display base
clock or DCLKI input can be used for this sampling clock. Also, by using the
chroma-key function, superimpose is performed with external circuitry as
follows:
External Sync
Enable
Hsync In
Vsync In
EO In
3 states
buffer
Hsync Out
Vsync Out
EO Out
HSYNC
ESY bit
Display Timming
Generator
C
W
C
M
EO
B
Cursor 0
Cursor 1
CKM bit
MB86290A
Analog
RGB In
KEYC
register
Compare
GV
Video SW
(Pedestal Clump Input)
Superimposed
Analog
RGB Out
Analog
RGB
Out
Fig. 5.2 Example of External Synchronization Circuit
The external synchronous mode is set using the ESY bit of the DCM register.
When the external synchronous mode is set, the HSYNC, VSYNC, and EO
pins of the MB86290A are placed in the input mode. After this, supply
external sync signals by using the tristate buffer. Also, when exiting from the
external synchronous mode, cut the external synchronous input and then set
the internal ESY bit of the MB86290A to OFF.
With the MB86290A sync signal output set to ON, avoid setting the buffer for
external sync signals to ON. Use the above procedure to control so that the
concurrent-ON duration will not occur.
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