MB86290A Datasheet, PDF (132/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

MDR3 (Mode Register for Texture)
DrawBaseAddress + 42Ch
Register address
Bit #
Bit field name
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 _{15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0}
TAB
TBL
TWS TWT
TF
TC
TBU
R/W
RW
RW
RW RW
RW
RW
RW
Default
00
00
00
00
0
0
0
This register controls the texture mapping mode.
Bit 0
TBU (Texture Buffer)
Selects texture memory (internal buffer always used in tiling)
0
External Graphics Memory
1
Internal texture buffer
Bit 3
TC (Texture coordinates Correct)
Controls perspective correction mode
0
Disable
1
Enable
Bit 5
TF (Texture Filtering)
Sets texture filtering mode
0
Point sampling
1
Bi-linear filtering
Bits 9-8
TWT (Texture Wrap T)
Set texture T-coordinate wrapping mode
00 Repeat
01 Cramp
10 Border
11 Reserved
Bits 11-10
TWS (Texture Wrap S)
Set texture S coordinate wrapping mode
00 Repeat
01 Cramp
10 Border
11 Reserved
Bits 17-16
TBL (Texture Blend mode)
Set texture blending mode
00 Decal
01 Modulate
10 Stencil
11 Reserved
Bits 21-20
TAB (Texture Alpha Blend mode)
Set texture alpha blending mode. The stencil alpha mode is used only when the BM bits in the MDR1
register are set to 01 (alpha blending). If any other mode is set at the BM bit field, the stencil alpha
mode is treated as the stencil mode.
00 Normal
01 Stencil
10 Stencil alpha
11 Reserved
132