MB86290A Datasheet, PDF (153/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

8.1.4 SH4 Single-address DMA Write (Transfer of 1 Long Word)
BCLKIN
D[31:0]
DREQ
DRACK
DTACK
Bus cycle
Acceptance
CPU
Acceptance
Acceptance
DMAC
*1
DMAC
CPU *1
{: DREQ sampling and channel priority determination for SH mode (DREQ = level
detection)
*1: In the cycle steal mode, even when DREQ is already asserted at the 2nd
DREQ sampling, the right to use the bus is returned to the CPU once. In the
burst mode, DMAC secures the right to use the bus unless DREQ is negated.
Fig. 8.4 SH4 Single-address DMA Write (Transfer of 1 Long Word)
The MB86290A writes data according to the DTACK assert timing. When
data cannot be received, the DREQ signal is automatically negated. And
then the DREQ signal is reasserted as soon as data becomes ready to be
received.
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