MB86290A Datasheet, PDF (95/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

DRM (DMA Request Mask)
Register address ^{HostBaseAddress + 05h}
Bit #
7
6
Bit field name
R/W
Default
5
4
3
Reserved
R0
0
2
1
0
DRM
RW
0
This register controls the DMA request to the host CPU. Setting 1 at this
register tentatively masks the DMA request. The DMA request is restarted
when 0 is set at this register.
DST (DMA STatus)
Register address ^{HostBaseAddress + 06h}
Bit #
7
6
Bit field name
R/W
Default
5
4
3
Reserved
R0
0
2
1
0
DST
R
0
This register indicates the DMA status. DST is set to 1 during DMA transfer.
This state is cleared to 0 when the DMA transfer is completed.
DTS (DMA Transfer Stop)
HostBaseAddress + 08h
Register address
Bit #
7
6
Bit field name
R/W
Default
5
4
3
Reserved
R0
0
2
1
0
DTS
RW
0
This register suspends DMA transfer. An ongoing DMA transfer is
suspended by setting DTS to 1.
LSTA (displayList transfer STAtus)
HostBaseAddress + 10h
Register address
Bit #
7
6
Bit field name
R/W
Default
5
4
3
Reserved
R0
0
2
1
0
LSTA
R
0
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