MB86290A Datasheet, PDF (122/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

MLTC (ML-layer Transparent Control)
Register address ^{DisplayBaseAddress + C2h}
Bit #
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit field name MLZT
MLTC
R/W
RW
RW
Default
0
Don’t care
This register controls the transparent color setting for the ML-layer. When
both MLTC and MLZT are set to 0, color 0 is displayed in black (not
transparent).
Bits 14-0 MLTC (ML-layer Transparent Color)
Set color code of transparent color used in ML-layer. Bits 7-0 used in indirect color mode.
Bit 15
MLZT (ML-layer Zero Transparency)
Sets treatment for code 0 in ML-layer
0
Code 0 not transparent color
1
Code 0 transparent color
CPAL0-255 (C-layer Pallet 0-255)
DisplayBaseAddress + 400h -- DisplayBaseAddress + 7FFh
Register address
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
A
R
G
B
R/W
RW
R0
RW
R0
RW
R0
RW
R0
Default
Don’
t
care
0000000
Don’t care
00
Don’t care
00
Don’t care
00
These are color pallet registers for Console layer and cursors. In the indirect
color mode, a color code in the display field indicates the pallet register
number (pallet entry number), and the color information set in that entry is
applied as the display color of that pixel.
Bits 7-2
B (Blue)
Set blue color element
Bit 15-10
G (Green)
Set green color element
Bits 23-18
R (Red)
Set red color element
Bit 31
A (Alpha)
When blending mode used, color blended with B/M/W layer pixel color according to blending ratio for
pixel of C layer with bit = 1. Alpha blending mode ignored when used as cursor color.
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