MB86290A Datasheet, PDF (134/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

FBR (Frame buffer Base)
Register address
DrawBaseAddress + 440h
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FBASE
RW
R0
Don’t care
0
This register controls the base address of the drawing frame memory.
XRES (X Resolution)
Register address
DrawBaseAddress + 444h
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XRES
RW
Don’t care
This register controls the drawing frame horizontal resolution.
ZBR (Z-buffer Base)
Register address
DrawBaseAddress + 448h
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ZBASE
RW
R0
Don’t care
0
This register controls the Z-buffer base address.
TBR (Texture memory Base)
Register address
DrawBaseAddress + 44Ch
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBASE
RW
R0
Don’t care
0
This register controls the texture memory base address.
PFBR (2D Polygon Flag-Buffer Base)
Register address
DrawBaseAddress + 450h
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PFBASE
RW
R0
Don’t care
0
This register controls the polygon flag buffer base address.
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