MB86290A Datasheet, PDF (33/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

3.3.3 Bus Mode
MB86290A supports the DMA transfer cycle steal mode and burst mode.
Either mode is selected by setting to the external DMA mode.
Cycle steal mode (In the V832 m ode, the burst m ode is called the single transfer
m o de .)
In the cycle steal mode, the bus right is transferred back to the host CPU at
every DMA transaction unit. The DMA transaction unit is either 1 double-
word (32 bits) or 8 double-words (32 B).
Burst mode (In the V832 m ode, the burst m o de is called the dem and transfer m o de.)
When DMA transfer is started, the right to use the bus is acquired and the
transfer begins. The data transfer unit can be selected from between the 1
double word (32 bits) and 8 double words (32 B).
Note: When performing DMA transfer in the dual-address mode, a function
for automatically negating DREQ is provided based on the setting of
the DBM register.
3.3.4 DMA Transfer Request
♦ Single-address mode
DMA is started when the MB86290A issues an external request to
DMAC of the host processor.
Set the transfer count in the transfer count register of the MB86290A
and then issue DREQ.
Fix the CPU destination address to the FIFO address.
♦ Dual-address mode
DMA is started by two procedures: the MB86290A issues an external
request to DMAC of the host processor, or the CPU itself is started
(auto request mode, etc.). Set the transfer count in the transfer count
register of MB86290A and then issue DREQ.
Note: The V832 mode requires no setting of the transfer count register.
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