MB86290A Datasheet, PDF (162/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

8.2.2 Timing of Read Access to Different Row Addresses
MCLKO
TRAS
TRP
MRAS
MCAS
TRCD
MWE
MA
ROW
MD
COL
CL
DATA
DQM
ROW: Row Address
COL: Column Address
DATA: READ DATA
TRAS: RAS Active Time
TRCD: RAS to CAS Delay Time
CL: CAS Latency
TRCD
ROW
COL
CL
DATA
TRP• RFAS Precharge Time
Note: This timing is used when CL2 is
operating.
Fig. 8.2.1 Timing of Read Access to Different Row Addresses
This timing diagram shows that different row addresses of SDRAM are read-
accessed from the MB86290A. An SDRAM page boundary is located between
the address to be read first and the address to be read next. Consequently,
the Precharge command is issued at the timing that meets the TRAS
condition, and then after TRP has elapsed, the ACTV command is reissued
and the Read command is issued.
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