MB86290A Datasheet, PDF (124/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

7.1.4 Draw Control Registers
CTR (Control Register)
Register address ^{DrawBaseAddress + 400h}
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FO PE CE
FCNT
NF FF FE
SS
DS
PS
RW RW RW
R
RRR
R
R
R
000
100000
001
00
00
00
This register indicates draw flags and status. Bits 24-22 are not cleared
until 0 is set.
Bits 1-0
PS (Pixel engine Status )
Indicate status of pixel engine unit
00 Idle
01 Busy
10 Reserved
11 Reserved
Bits 5-4
DS (DDA Status)
Indicate status of DDA
00 Idle
01 Busy
10 Reserved
11 Reserved
Bits 9-8
SS (Setup Status)
Indicate status of Set up unit
00 Idle
01 Busy
10 Reserved
11 Reserved
Bit 12
Bit 13
Bit 14
FE (FIFO Empty)
Indicates status of display list FIFO
0
Valid data
1
No valid data
FF (FIFO Full)
Indicates fullness of display list FIFO
0
Not full
1
Full
NF (FIFO Near Full)
Indicates entries of display list FIFO
0
Empty entries equal to or more than half
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