MB86290A Datasheet, PDF (157/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

BCLKIN
DMARQ
DMAAK
8.1.8 V832 DMA Transfer
For the MB86290A, the read/write operation is performed according to the SRAM
protocol.
A[23:2]
D[31:0]
Source address
Read
Destination address
Write
Source address
Read
Destination address
Write
Fig. 8.8 V832 DMA Transfer
During DMA transfer, the DREQ signal is kept asserted until the transfer
ends by default. Consequently, to negate the DREQ signal when the
MB86290A cannot return the Ready signal immediately, set the DBM
register.
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