MB86290A Datasheet, PDF (108/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

WOA (W-layer Origin Address)
Register address ^{DisplayBaseAddress + 34h}
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserve
R0
0
WOA
RW
Don’t care
R0
0000
This register controls the base address of the logical frame of the Window
layer. Since the lowest 4-bits are fixed to 0, this address is 16-byte aligned.
WDA (W-layer Display Address)
DisplayBaseAddress + 38h
Register address
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserve
R0
0
WDA
RW
Don’t care
This register controls the base address of the display field of the Window
layer. Since only the direct color mode is applicable to the Window layer, the
LSB is fixed to 0 and this address is 2-byte aligned.
MLM (ML-layer Mode)
DisplayBaseAddress + 40h
Register address
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name ^MLC MLFLP
Reserve
MLW
Reserve
MLH
R/W
RW _R0
R0
RW
R0
RW
Default
00
0
Don’t care
0
Don’t care
Bits 11-0 MLH (ML-layer Height)
Set height of Middle Left (ML) layer logical frame size in raster units. Setting + 1 is the height.
Bits 23-16
MLW (ML-layer memory Width)
Set width of Middle Left (ML) layer logical frame size in 64-byte units
Bits 30-29
MLFLP (ML-layer Flip mode)
Set flipping mode for Middle Left (ML) layer
00 Display frame 0
01 Display frame 1
10 Switch frame 0 and 1 back and forth
11 Reserved
Bit 31
MLC (ML-layer Color mode)
Sets color mode for Middle Left (ML) layer
0
Indirect color mode (8 bits/pixel)
1
Direct color mode (16 bits/pixel)
108