MB86290A Datasheet, PDF (32/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

3.3 DMA Transfer
3.3.1 Data Transfer Unit
DMA transfer is performed in double-word (32 bit) units or 8 double-word (32
Byte) units. Byte and word access is not supported.
Note: 8 double-word transfer is supported only in the SH4 mode.
3.3.2 Address Mode
Dual address mode
DMA is performed at memory-to-memory transfer between host memory
(source) and MB86290A internal registers, memory, or external memory
(destination). Both the host memory address and destination address is used. In
the SH4 mode, the 1 double-word transfer (32 bits) and 8 double-word transfer (32
bytes) can be used.
When the CPU transfer destination address is fixed, data can also be
transferred to the FIFO interface. However, in this case, even the SH4 mode
supports only the 1 double-word transfer.
Note: The SH3 mode supports the direct address mode; it does not support
the indirect address mode.
Single address mode (FIFO interface)
DMA is performed between host memory (source) and FIFO (destination).
Address output from the host CPU is only applied to designate the source,
and the data output from the host memory is transferred to the FIFO using
the DACK signal. In this mode, data read from the host memory and data
write to the FIFO occur in the same bus cycle. This mode does not support
data write to the host memory. When the FIFO is full, the DREQ signal is
tentatively negated and the DMA transfer is suspended until the FIFO has
room for more data.
The 1 double-word transfer (32 bits) and the 8 double-word transfer (32 Bytes) can
be used.
Note: The single-address mode is supported only in the SH4 mode.
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