MB86290A Datasheet, PDF (111/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

MROA0 (MR-layer Origin Address 0)
DisplayBaseAddress + 5Ch
Register address
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserve
R0
0
MROA0
RW
Don’t care
R0
0000
This register controls the base address of the logical frame (frame0) of the
Middle Right (MR) layer. Since the lowest 4 bits are fixed to 0, this address is
16-byte aligned.
MRDA0 (MR-layer Display Address 0)
DisplayBaseAddress + 60h
Register address
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserve
R0
0
MRDA0
RW
Don’t care
This register controls the base address of the Middle Left (ML) layer display
field in frame0. When the direct color mode is used, the LSB is fixed to 0 and
this address is 2-byte aligned.
MROA1 (MR-layer Origin Address 1)
DisplayBaseAddress + 64h
Register address
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserve
R0
0
MROA1
RW
Don’t care
R0
0000
This register controls the base address of the logical frame (frame1) of the
Middle Right (MR) layer. Since the lowest 4 bits are fixed to 0, this address is
16-byte aligned.
MRDA1 (MR-layer Display Address 1)
DisplayBaseAddress + 68h
Register address
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserve
R0
0
MRDA1
RW
Don’t care
This register controls the base address of the Middle Right (MR) layer display
field in frame1. When the direct color mode is used, the LSB is fixed to 0 and
this address is 2-byte aligned.
MRDX (MR-layer Display position X)
DisplayBaseAddress + 6Ch
Register address
Bit #
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit field name
Reserved
MRDX
R/W
R0
RW
Default
0
Don’t care
111