MB86290A Datasheet, PDF (133/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

MDR4 (Mode Register for BLT)
Register address ^{DrawBaseAddress + 430h}
Bit #
Bit field name
R/W
Default
31 30 29 ²⁸ 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 ⁸ 7 6 5 4 3 2 1 0
LOG
BM
TI
RW
RW
RW
0011
00
0
This register controls the BitBLT. Mode.
Bits 8-7
BM (Blend Mode)
Set blend mode
00 Normal (source copy)
01 Reserved
10 Logical calculation enable
11 Reserved
Bits 12-9
LOG (Logical operation)
Set logical calculation type
0000 CLEAR
0001 AND
0010 AND REVERSE
0011 COPY
0100 AND INVERTED
0101 NOP
0110 XOR
0111 OR
1000 NOR
1001 Reserved
1010 INVERT
1011 OR REVERSE
1100 COPY INVERTED
1101 OR INVERTED
1110 NAND
1111 SET
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