MB86290A Datasheet, PDF (158/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

8.1.9 SH4 Single-address DMA Transfer End Timing
BCLKIN
D[31:0]
DREQ
DRACK
DTACK
Acceptance
Acceptance
Last data
{: DREQ sampling and channel priority determination for SH mode (DREQ = level
detection)
Fig. 8.9 SH4 Single-address DMA Transfer End Timing
DREQ is negated three cycles after DRACK is written as the last data.
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