MB86290A Datasheet, PDF (96/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

This register indicates the DisplayList transfer status from Graphics Memory.
LSTA is set to 1 while DisplayList transfer is in progress. This status is
cleared to 0 when DisplayList transfer is completed
DRQ (DMA ReQquest)
HostBaseAddress + 18h
Register address
Bit #
7
6
Bit field name
R/W
Default
5
4
3
Reserved
R0
0
2
1
0
DRQ
RW1
0
Starts sending external DMA request signal
DMA transfer using the external DMA request handshake is triggered by
setting DRQ to 1. The external DREQ signal is not asserted when DMA is
masked by the DRM register. This register cannot be set to 0. When DMA
transfer is completed, this status is cleared automatically to 0.
IST (Interrupt STatus)
Register address ^{HostBaseAddress + 20h}
Bit #
7
6
5
Bit field name
Reserved
R/W
R0
Default
0
4
FSYNC
RW0
0
3
SYNCERR
RW0
0
2
VSYNC
RW0
0
1
CEND
RW0
0
0
CERR
RW0
0
This register indicates the current interrupt status. When an interrupt
request to the host CPU is asserted, this register displays 1. The interrupt
status is cleared by setting 0 at this register.
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
CERR (Command Error Flag)
Draws command execution error interrupt
CEND (Command END)
Draws command complete interrupt
VSYNC (Vertical Sync.)
VSYNC detection interrupt
FSYNC (Frame Sync.)
Indicates frame synchronization interrupt
SYNCERR (Sync. Error)
Indicates external synchronization error interrupt
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